This invention is related to a patent application filed on Apr. 6, 1995, by George Meyer. That patent application was given an application Ser. No. of 08/417,524 and is assigned to the same assignee as the present invention.
This invention relates, in general, to semiconductor devices, and more particularly to semiconductor devices having a planarized trench isolation structure.
Some advanced semiconductor devices employ trench isolation as a method for electrically isolating a semiconductor device from neighboring structures. In short, trench isolation structures are formed by first patterning a masking layer on a semiconductor substrate. A reactive ion etch (RIE) is then used to remove exposed portions of the semiconductor substrate to form trench structures. The trenches are then filled with a non-conductive material such as silicon dioxide. Before the formation of the semiconductor device can continue, the non-conductive material must be polished to planarize the surface of the semiconductor substrate while maintaining a filled trench structure.
The density of the trench structures, however, causes a dishing problem when conventional polishing techniques such as chemical and mechanical polishing (CMP) are used. As the density of the trench pattern increases, the polish rate in that area decreases due to the presence of the additional material that must be removed. As a result, isolated trench structures will polish must faster than an area of the substrate that has a higher density of trench structures. This will cause the non-conductive material in the isolated structures to polish further than the denser areas thereby resulting in polishing non-uniformity (referred to as "dishing").
One method used to correct for the dishing problem is to first etch the conductive material with a reactive ion etch (RIE) using a pattern that is the n-layer or opposite pattern used to originally form the trenches. Thus the bulk of the non-conductive material is removed with the RIE etch prior to the polish process. This n-layer technique, however, requires and additional photolithographic mask and processing step and is prone to forming particle defects that will reduce the yield of the semiconductor device.
Another technique that attempts to improve the planarity of the non-conductive layer is to form dummy or tile structures around the device. This is done by simply inserting dummy structures randomly through the device in an attempt to equalize the polishing rate across the substrate. This technique, however, can cause shorting between various well structures or between interconnect structures that are used to form the device. This method can also affect the performance of the device by inserting large structures that change the capacitance of the device.
By now it should be appreciated that it would be advantageous to provide a method for improving the planarization of a non-conductive material when trench isolation is employed. It would also be advantageous if the method did not require the use of an additional photolithographic mask or electrically short circuit conductive portions of a semiconductor device.